and DDRII spec

I got this info @ JC's:
"Improved I/O structure
* Mult-drop memory configurations: 400 Mbits/sec/pin
* * 64 bit memory system - 3.2 GBytes/seccc
* Point to point memory configurations: 800 Mbit/sec/pin
* * 64 bit memory system - 6.4 GBytes/sec
Dram core utilizes a prefetch of 4
* Decreases frequency of dram core relative needed to support increased data rate
* * Dram core runs at 1/4 data bus frequency
* Improves yield at DDR II's high frequency data rate
* Lower core power
Commands can be valid on any rising edge of clock
* Preserves command bus utilization
* * Dram command bus runs at 1/2 data bus frequency
Posted CAS
* Increases command bus utilization
Write latency equals read latency minus one
* Increases data bus tilization
Low latency enhancements
* Exploring Virtual Channel
* Exploring ESDRAM Lite
Elimination of interrupt commands
* Reduces test costs
* Increses yield due to elimination of speed critical path
Burst 4 only
* Reduce test costs
Elimination of 1/2 cycle latencies
* Reduce test costs
Device and DIMM Pinous optimized for low cost motherboard and DIMM routing"
Please mind that this was probably an early document, so the final DDR II spec is possibly somewhat different.